The size of semiconductor devices continues to shrink as advances are made in semiconductor manufacturing technology. In particular, transistor junction depths continue to become shallower. Secondary ion mass spectroscopy (SIMS) and electron beam (E-Beam) shallow probe analysis and X-Ray Diffraction (XRD) are prior art techniques for testing semiconductor wafers. The size of test structures on a semiconductor wafer that are used as locations for conducting such tests also continues to shrink.
Prior art test structures located at the scribe lines of a semiconductor wafer are unable to provide adequate areas to perform (1) the SIMS test and analysis or (2) the E-Beam test and analysis or (3) the X-Ray diffraction test and analysis with the accuracy and precision required by these processes. That is, the prior art test structures located at the scribe lines can not provide an adequate area to properly perform the SIMS/E-Beam/XRD tests on a semiconductor wafer.
Because junction depths are becoming shallower, the primary ion and electron beam energies of SIMS and of E-Beam probes must be correspondingly lower. This causes the SIMS and E-beam probes to have higher levels of beam aberration. These lower ion and electron beam energies and higher levels of beam aberration require a test area that is at least one hundred microns square. The required test area is at least one hundred microns (100 μm) by one hundred microns (100 μm). A micron is one millionth of a meter (1 μm=10−6 m).
The SIMS test is a destructive technique. Any attempt to use it for scribe line structures near product wafer areas (or on individual test structures created within a die) can be costly. In addition, it is necessary to provide protective masks. The risk of contamination is also present.
Although claimed to be non-destructive, the E-Beam test and the XRD test cannot reasonably be used for testing near product wafer areas because it is possible that charges may build up while the electron beam or the X-ray beam is in operation. The accumulated charges may be very damaging to the nearby circuitry of the integrated circuit die.
Therefore, there is a need in the art for a system and method for identifying and using other types of areas in a semiconductor wafer to create structures for the testing and analysis of the semiconductor wafer using either a SIMS test and analysis, an E-Beam test and analysis, or an X-ray diffraction test and analysis.